View SST-SALEM-3T_1308421.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 a adsst-em-3035 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 salem three-phase electronic energy meter features iec 687, class 0.5 and class 0.2 accuracy ansi c12.1 iec 1268, requirements for reactive power configurable as import/export or import only simultaneous measurement of: active power and energy?mport and export reactive power and energy apparent power power factor for individual phases and total frequency rms voltage for all phases rms current for all phases harmonic analysis for voltage and current all odd harmonics up to 21st order interface with a general purpose microcontroller user-friendly calibration of gain offset and phase and nonlinearity compensation on cts (patent pending) two programmable output e-pulses programmable e-pulse constant from 1,000 pulses/kwh to 20,000 pulses/kwh 15 khz sampling frequency tamper-proof metering single 5 v supply general description the adsst-em-3035 chipset consists of a fast and accurate 6 channel, 16-bit sigma-delta analog-to-digital converter adsst-73360ar (adc), an efficient digital signal processor adsst-2185kst-133 (dsp), and metering software. the adc and dsp are interfaced together to simultaneously acquire voltage and current samples on all the three phases and perform mathematically intensive computations to accurately calculate the powers, energies, instantaneous quantities, and harmonics. the chipset could be interfaced to any general-purpose micropro- cessor to develop state of the art polyphase or tri-vector energy metering solution in accordance with iec 1036, iec 687, or ansi c12.1. all calibrations are done in digital domain and no trimming potentiometers are required. functional block diagram smps spi bus dsp adc adsst-em-3035 c hipset ct ct ct resistor block rtc flash rs-232 opto c lcd display butt ons salem is a registered trademark of analog devices, inc.
rev. 0 adsst-em-3035 e2e adsst-2185kst-133 (dsp) specification features 30 ns instruction cycle 33 mips sustained performance single-cycle instruction execution single-cycle context switch three-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 100 cycle recovery from power-down condition low power dissipation in idle mode adsp-2100 family code compatible, with instruction set extensions 40 kbytes of on-chip ram, configured as 8 kwords on-chip program memory ram and 8 kwords on-chip data memory ram dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead tqfp 16-bit internal dma port for high speed access to on- chip memory (mode selectable) 4 mbytes byte memory interface for storage of data tables and program overlays 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) i/o memory interface with 2048 locations supports parallel peripherals (mode selectable) programmable memory strobe and separate i/o memory space permits glueless system design (mode selectable) programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling uart emulation through software sport reconfiguration ice-port emulator interface supports debugging in final systems general description the adsst-2185kst-133 is a single-chip microcomputer optimized for digital signal processing (dsp) and other high speed numeric processing applications. the adsst-2185kst-133 combines the adsp-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the adsst-2185kst-133 integrates 40 kbytes of on-chip memory configured as 8 kwords (24-bit) of program ram and 8 kwords (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. the adsst-2185kst-133 is available in a 100-lead tqfp package. in addition, the adsst-2185kst-133 supports instructions that include bit manipulations, bit set, bit clear, bit toggle, bit test new alu constants, new multiplication instruction (x squared), biased rounding, result free alu operations, i/o memory trans- fers, and global interrupt masking for increased flexibility. fabricated in a high speed, double metal, low power, cmos process, the adsst-2185kst-133 operates with a 25 ns instruction cycle time. every instruction can execute in a single processor cycle. the adsst-2185kst-133?s flexible architecture and com- prehensive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle, the adsst-2185kst-133 can: ? ? ? ? ? ?
rev. 0 adsst-em-3035 ? architecture overview the adsst-2185kst-133 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single processor cycle. the adsst-2185kst-133 assembly language uses an algebraic syntax for ease of coding and read- ability. a comprehensive set of development tools supports program development. figure 1 is an overall block diagram of the adsst-2185kst-133. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. the internal result (r) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these com- putational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the adsst-2185kst-133 executes looped code with zero overhead. no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simul- taneous dual operand fetches from data memory and program memory. each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post- modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permitting the adsst-2185kst-133 to fetch two operands in a single cycle, one from program memory and one from data memory. the adsst-2185kst-133 can fetch an operand from program memory and the next instruction in the same cycle. when configured in host mode, the adsst-2185kst-133 has a 16-bit internal dma port (idma port) for connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsp? on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with programmable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh , and bg ). one execution mode (go mode) allows the adsst-2185kst-133 to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the adsst-2185kst-133 can respond to 11 interrupts. there are up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal inter- rupts generated by the timer, the serial ports (sports), the byte dma port, and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hard- ware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the adsst-2185kst-133 provides up to 13 general purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the adsst-2185kst-133 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the adsst-2185kst-133 sports. for additional information on serial ports, refer to the adsp-2100 family user? manual , third edition. ? sports are bidirectional and have a separate, double-buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchro- nization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m-law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data-word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data-word. an interrupt is generated after a data buffer transfer.
rev. 0 adsst-em-3035 e4e ? ? irq0 irq1 iot p i p o reset 1i pri br 1i bri bg 1o bgo bgh 1o bgho dms 1o dmso pms 1o pmso ioms 1o mso bms 1o bmso cms 1o cm so rd 1o mreo wr 1o mreo irq2 p 1i els ir 1 irql0 p 1 i ls ir 1 irql1 p 1i ls i r 1 irqe p 1i es ir 1 p 1 io piop p2 m c 1i piopm sic dreset p1 m b 1i msic dreset ticmp p i p o p0m 1 i m sic dreset cli 2 i c qci tl clot 1 o pco sport0 io spiop sport1 io spiop irq1 0 els i 10 io 2 pwd 1i pdci pwdc 1 o pdco l0l1 o o l2 dd 1 i ddgd d gd ep io e otes 1 iiims dsp 2 sportdspscrs pd tdsst21st1100tqp t treset i
rev. 0 adsst-em-3035 e5e 100-lead tqfp package pinout 5 4 3 2 7 6 9 8 1 d19 d18 d17 d16 irqe p irql0 p gnd irql1 p dt0 ts0 sclk0 dd dt1o ts1 irq1 rs1 irq0 dr1i gnd sclk1 ereset reset d1 d1 d1 d12 gnd d11 d10 d dd gnd d d iwr d ird dial d is gnd dd d iack d2iad1 d1iad1 d0iad1 bg ebg br ebr aiad aiad gnd aiad aiad aiad aiad a10iad a11iad10 a12iad11 a1iad12 gnd clkin tal dd clkot gnd dd wr rd bms dms pms ioms cms 1 2 0 0 1 2 2 1 100 2 1 0 2 1 0 pin1 identiier topiew ns 2 2 2 2 0 1 2 0 1 2 0 11 10 1 1 1 1 1 1 20 1 22 21 12 2 2 2 adsst21kst1 irq2 p rs0 dr0 ems ee elot eclk elin eint aiad2 a2iad1 a1iad0 a0 pwdack bgh l0 l1 l2 d2 d22 d21 d20 gnd p1modeb gnd pwd dd p0modea p2modec p
rev. 0 adsst-em-3035 e6e system interface figure 2 shows typical basic system configurations with the adsst-2185kst-133, two serial devices, a byte-wide eprom and optional external program and data overlay memories (mode selectable). programmable wait state generation allows the proces- sor to connect easily to slow peripheral devices. the adsst- 2185kst-133 also provides four external interrupts and two serial ports, or six external interrupts and one serial port. host memory mode allows access to the full external data bus, but limits address- ing to a single address bit (a0). additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. serial device serial device system interface or controller 16 1 16 sclk1 rfs1 or irq0 ts1or irq1 dt1oro dr1ori sport1 sclk0 rs0 ts0 dt0 dr0 sport0 ird d iwr d is d iald iack d iad10 idmaport l02 p clkin tal addr0 da ta 2 bms ioms pms dms cms br bg bgh pwd pw dack adsst21 kst1 irq2 p irqe p irql0 p irql1 p modecp2 modebp1 modeap0 hostmemormode 12clock or crstal 12clock or crstal serial deice serial deice sclk1 rs1or irq0 ts1or irq1 dt1oro dr1ori sport1 sclk0 rs0 ts0 dt0 dr0 sport0 a0a21 data cs bte memor iospace peripherals cs data addr data addr 20locations o erla memor twok pmsegments twok dmsegments d 20 a 10 d 2 a 100 d 1 d 21 a 10 1 2 l02 p clkin tal addr10 da ta 20 bms ioms pms dms cms br bg bgh pwd adsst21 kst1 irq2 p irqe p irql0 p irql1 p modecp2 modebp1 modeap0 llmemormode pw dack 2bsi cs ettl adsst21kst1 tclkin t c adsp-2100 family user? manual , third edition, for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is connected to the processor's clkin input. when an external clock is used, the xtal input must be left unconnected. the adsst-2185kst-133 uses an input clock with a frequency equal to half the instruction rate; a 20.00 mhz input clock yields a 25 ns processor cycle (which is equivalent to 40 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the adsst-2185kst-133 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 3. capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor- grade crystal should be used. clkin xtal clkout dsp figure 3. external crystal connections a clock output (clkout) signal is generated by the processor at the processor? cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. reset the reset dsst 21st1t reset reset i reset t dd pll 2000clipll d reset o reset rsp t reset rc reset st msttw reset t 00000 roc g bg p m m m m dd s t mb 0 0 0
rev. 0 adsst-em-3035 ? k/b grade parameters test conditions min typ max unit v ih high-level input voltage 1, 2 @ v dd = max 2.0 v v ih high-level clkin voltage @ v dd = max 2.2 v v il low-level input voltage 1, 3 @ v dd = min 0.8 v v oh high-level output voltage 1, 4, 5 @ v dd = min i oh = ?.5 max 2.4 v @ v dd = min i oh = ?00 a 6 v dd ?0.3 v v ol low-level output voltage 1, 4, 5 @ v dd = min 0.4 v i ol = 2 ma i ih high-level input current 3 @ v dd = max v in = v dd max 10 a i il low-level input current 3 @ v dd = max v in = 0 v 10 a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 10 a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 10 a i dd supply current (idle) 9 @ v dd = 5.0 12.4 ma i dd supply current @ v ddint = 5.0 (dynamic) 10, 11 t amb = 25 c t ck = 30 ns 11 55 ma t ck = 25 ns 11 [65] ma c i input pin @ v in = 2.5 v, capacitance 3, 6, 12 f in = 1.0 mhz, t amb = 25 c8pf c o output pin @ v in = 2.5 v, capacitance 6, 7, 12, 13 f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0?23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2-0, bgh . 5 although specified for ttl outputs, all adsst-2185kst-133 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0?13, d0, d23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0, pf7. 8 0 v on br , clkin inactive. 9 idle refers to adsst-2185kst-133 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 12 applies to tqfp package type 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7.0 v input voltage . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range (ambient) . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 sec) tqfp . . . . . . . . . . . . . . . . 280 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. environmental conditions ambient temperature rating: t amb = t case ?(pd ca ) t case = case temperature in c pd = power dissipation in w ja = thermal resistance (junction-to-ambient) jc = thermal resistance (junction-to-case) ca = thermal resistance (case-to-ambient) package ja jc ca tqfp 50 c/w 2 c/w 48 c/w electrical characteristics
rev. 0 adsst-em-3035 e8e adsst-73360ar (adc) features six 16-bit a/d converters programmable input sample rate simultaneous sampling 76 db snr 64 ks/s maximum sample rate e83 db crosstalk low group delay (125 s typ per adc channel) programmable input gain flexible serial port which allows multiple devices to be connected in cascade single (2.7 v to 5.5 v) supply operation 80 mw max power consumption at 2.7 v on-chip reference 28-lead soic vinn1 vinp1 analog - conditioning sdi sdifs sclk refcap refout se reset sdos sdo mclk inn2 inp2 inn inp inn inp inn inp inn inp adsst0ar signal conditioning 0b pga decimator serial io port analog conditioning signal conditioning 0b pga decimator analog conditioning signal conditioning 0b pga decimator analog conditioning signal conditioning 0b pga decimator analog conditioning signal conditioning 0b pga decimator analog conditioning signal conditioning 0b pga decimator reerence bd generaldescription tadsst0ar i1ad bh e pga 0 bb tadsst0ar t adsst0ar a 12 t h2h1hh 1mh asport dsptsport dsp tadsst0ar2soic
rev. 0 adsst-em-3035 e9e specifications adsst-73360ar (avdd = 5 v 10%; dvdd = 5 v 10%; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f sclk = 8.192 mhz, f s = 8 khz; t a = t min to t max , unless otherwise noted 1 .) parameter min typ max unit test conditions/comments reference refcap absolute voltage, v refcap 1.25 v 5 ven = 0 2.5 v 5 ven = 1 refcap tc 50 ppm/ ? = = ? = = = = + = + + = = = = = = = = = ? =
rev. 0 adsst-em-3035 e10e parameter min typ max unit test conditions/comments logic inputs v inh , input high voltage v dd e 0.8 v dd v v inl , input low voltage 0 0.8 v i ih , input current e0.5 + = = + = = = + + + + + +
rev. 0 adsst-em-3035 e11e pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 adsst- 73360ar sdo mclk sclk reset dv dd dgnd agnd2 vinp2 vinn2 vinp1 vinn1 av dd 2 refcap refout sdofs sdifs sdi se agnd1 av dd 1 vinp6 vinn3 vinp3 vinn4 vinp4 vinn6 vinp5 vinn5 mnemonic function vinp1 analog input to the positive terminal of input channel 1 vinn1 analog input to the negative terminal of input channel 1 vinp2 analog input to the positive terminal of input channel 2 vinn2 analog input to the negative terminal of input channel 2 vinp3 analog input to the positive terminal of input channel 3 vinn3 analog input to the negative terminal of input channel 3 vinp4 analog input to the positive terminal of input channel 4 vinn4 analog input to the negative terminal of input channel 4 vinp5 analog input to the positive terminal of input channel 5 vinn5 analog input to the negative terminal of input channel 5 vinp6 analog input to the positive terminal of input channel 6 vinn6 analog input to the negative terminal of input channel 6 refout buffered refer ence output, which has a nominal value of 1.2 v or 2.4 v, the value being dependent on the status of bit 5 ven (crc:7). this pin can be overdriven by an external reference if required. refcap a bypass capacitor to agnd2 of 0.1 reset lrst scl osc dsst0ri sporttscl mcl t mcl mcimcl sdo sdodsst0rb sclsdo se sdos sosdostt scl msbsdos sclsdos se sd is sisdistt scl msbsdis scl se sdi sdidsst0rb sclsdi se se sporte sportwsedsp sport scl wse sport seh gd1 gc dd 1 psc pictiodescriptios
rev. 0 adsst-em-3035 e12e grounding and layout analog ground digital ground figure 5. grounding and layout since the analog inputs to the adsst-73360ar are differential, most of the voltages in the analog modulator are common-mode voltages. the excellent common-mode rejection of the part will remove common-mode noise on these inputs. the analog and digital supplies of the adsst-73360ar are independent and separately pinned out to minimize coupling between analog and digital sections of the device. the digital filters on the encoder section will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. the digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. however, because the resolution of the adsst- 73360lar adc is high, and the noise levels from the adsst-73360ar are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the adsst-73360ar should be designed so the analog and digital sections are sepa- rated and confined to certain sections of the board. the adsst-73360ar pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package. this facilitates the use of ground planes that can be easily separated, as shown in figure 5. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place. if this connection is close to the device, it is recommended to use a ferrite bead inductor as shown in figure 5. avoid running digital lines under the device for they will couple noise onto the die. the analog ground plane should be allowed to run under the adsst-73360ar to avoid noise coupling. the power supply lines to the adsst-73360ar should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a micro-strip technique is by far the best but is not always possible with a double-sided board. in this tech- nique, the component side of the board is dedicated to ground planes while signals are placed on the other side. good decoupling is important when using high speed devices. all analog and digital supplies should be decoupled to agnd and dgnd respectively, with 0.1 ? ? ?
rev. 0 adsst-em-3035 e13e in the sequence of booting the dsp, it has to be loaded with an object code into the internal program memory. the byte wide memory boot code file has the following structure: a) 32 words or 96 bytes of the initial header, b)81 words or 243 bytes for initializing bdma and associated registers, c) 6712 words or 20136 bytes of program code. d0ed7 clock d0ed7 flash v dd d pr clk o br reset dd1 d0d p p p bms c dsp l sabldsp pm wdspmamb mc tdsp 2 2tdsp 1a 1t dspbdma i dsp201 11 a201 tdsp ? ? ? ? ? ? ?
rev. 0 adsst-em-3035 e14e serial peripheral interface (spi) and control the dsp and the microcontroller are interfaced through serial peripheral interface (spi). the microcontroller is always config- ured as a master and the dsp as a slave. framing signal rfs tf dr dt sclk fl2 dsp control spi transmit spi receive clk interrupt dsp microcontroller figure 8. serial peripheral interface and control spi operation there are two modes of communication between dsp and microcontroller. ? ? ? ? ? ? +
rev. 0 adsst-em-3035 e15e table iii. data transfer to dsp on power-up initialization gain constants and dc offsets value defaults r phase voltage gain 2 4000h y phase voltage gain 2 4000h b phase voltage gain 2 4000h r phase current low gain 2 4000h y phase current low gain 2 4000h b phase current low gain 2 4000h r phase current high gain 2 4000h y phase current high gain 2 4000h b phase current high gain 2 4000h r phase voltage dc offset 2 0 y phase voltage dc offset 2 0 b phase voltage dc offset 2 0 r phase current low gain dc offset 2 0 y phase current low gain dc offset 2 0 b phase current low gain dc offset 2 0 r phase current high gain dc offset 2 0 y phase current high gain dc offset 2 0 b phase current high gain dc offset 2 0 e-pulse (type) * energy pulse e ? ? ?
rev. 0 adsst-em-3035 ?6 data from dsp on spi bus byte(s) b phase channel_present 1 r phase current division flagunits_flag_r 1 y phase current division flagunits_flag_y 1 b phase current division flagunits_flag_b 1 r phase negative power flag 1 y phase negative power flag 1 b phase negative power flag 1 r phase (induc/cap power flag) 1 y phase (induc/cap power flag) 1 b phase (induc/cap power flag) 1 gain contrasts and dc offsets r phase voltage gain 2 y phase voltage gain 2 b phase voltage gain 2 r phase current low gain 2 y phase current low gain 2 b phase current low gain 2 r phase current high gain 2 y phase current high gain 2 b phase current high gain 2 r phase voltage dc offset 2 y phase voltage dc offset 2 b phase voltage dc offset 2 r phase current low gain dc offset 2 y phase current low gain dc offset 2 b phase current low gain dc offset 2 r phase current high gain dc offset 2 y phase current high gain dc offset 2 b phase current high gain dc offset 2 dc_offset calibration done (efh) 1 total negative power flag 1 total inductive capacitive flag 1 harmonic analysis data (all odd harmonics sequenced from fundamental to 21st order, total 11 harmonics of 2 bytes each) r phase voltage components magnitude 2 11 = 22 r phase current components magnitude 22 r phase voltage components phase 22 r phase current components phase 22 y phase voltage components magnitude 22 y phase current components magnitude 22 y phase voltage components phase 22 y phase current components phase 22 b phase voltage components magnitude 22 b phase current components magnitude 22 b phase voltage components phase 22 b phase current components phase 22 table v. interpretation of the voltage data phase voltage data from dsp hex (2 byte) decimal voltage 5a10h 23056 230.56 v table vi. interpretation of the current data line current data unit from dsp flag_x hex (2 byte) decimal (x = r/y/b) current 278bh 10123 1 1.0123 a 278bh 10123 0 10.123 a frequency data from dsp the frequency data is with two decimal places. this means that the value has to be divided by 100 to get the frequency. for example, if dsp data = 139fh (decimal value = 5023), then the frequency is 50.23 hz interpretation of the power data as in the case of current and voltages, described above, all the power data supplied by dsp has to be interpreted, as shown in table vii. the data received from the dsp is in a 4-byte format. the least significant word comes first and the most significant word comes last, e.g., 000d1c4a will come as 1c4a000d and this word reversal has to be performed by the controller. table vii. interpretation of the power data power data from dsp hex (4-byte) decimal power 000d1c4a 859210 859.210 w interpretation of the power factor data the dsp data for power factor has a resolution up to four deci- mal places. to get the value of power factor the dsp data has to be divided by 10,000. table viii. interpretation of the power factor data power factor data from dsp hex (2-byte) decimal power factor 1388h 5000 0.5 interpretation of the energy data the dsp data for energy has a resolution up to four decimal places. to get the value of energy the dsp data has to be divided by 10,000. table ix. interpretation of the energy data energy data from dsp hex (4-byte) decimal energy 000d1c4ah 859210 85.9210 kwh
rev. 0 adsst-em-3035 e17e interpretation of harmonics data each harmonic data from dsp is two byte wide. the voltage and phase angle values have a resolution of up to second deci- mal place and the current has up to third decimal place. input section phase voltage 100 to adc v cc gnd 0.01 f 82 neutral line current 1m 3.3k 0.001 f 100 * value may change according gnd pdsp to adc figure 11. input section adsst-73360ar has an input range of v ref + (v ref ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? = ? = =
rev. 0 adsst-em-3035 ?8 table x. dc offset calibration data command from setup input dc-offset microcontrolled voltage and calibration in hex current offset 0xef v = nominal calibration voltage (all three phases) i = 0 the microcontroller now issues 0x45h command on spi to the dsp. the dsp sends back table iv. this table will contain new dc-offset coefficients. the microcontroller should store these coefficients. procedure ? power up the meter with nominal voltage ? give command for calculation of the coefficient (efh) to dsp on spi. ? receive the coefficient by sending ox45 on spi after waiting at least 1s. ? store the coefficient phase compensation the adsst-em-3035 employs a patent pending algorithm for phase compensation and non-linearity. this also reduces the cost of the end product by reducing the cost of the sensing ele- ments i.e., ct. to compensate for the phase non-linearity in cts, the compensation is performed at three current ranges. the three current ranges for calibration are: ? 20 a > i 1 > 7 a ? 7 a > i 2 > 1.5 a ? 1.5 a > i 3 > 0 a procedure ? the adsstcomp.exe supplied with the chipset is an executable file for calculation of the phase compensation coeffi cients. ? set the voltage equal to 230 v which is the nominal voltage at all phases. ? inject i 1 current at 0.5 inductive (60 lagging) in all phases. ? the chipset performs the harmonic analysis by providing information about the magnitude and phase angle for all odd harmonics sequenced from fundamental to 21st order. the dsp sends the phase angle information along with other data as described in table iv after sending the command 0x45. ? the value of the phase angle for line current a, b, and c is available at the locations 283, 371, and 459 respectively (say p a , p b , p c ) in the data stream sent by the dsp. ? calculate the normalized lag value (l a , l b , l c ) for each phase as under : l p a a = + 60 120 2 ? . (1) l p b b = + 60 120 2 ? . (2) l p c c = + 60 120 2 ? . (3) ? run adsstcomp.exe on pc ? feed the normalized lag value during the execution of adsstcomp.exe. ? the adsstcomp.exe will provide six coefficients for each phase and the size of each coefficient is 2 bytes. ? the phase compensation should be performed for the three currents on each phase. these coefficients must be stored in a suitable location such that dsp can get these coefficients on power up in the same sequence as shown in table iii. configuration of output e-pulses the adsst-em-3035 chipset provides two pulse outputs ? configurable for active energy or apparent energy ? reactive energy ? table iii gives the default conditions and configuration for first e-pulse. ? the e-pulse constant is variable from 1,000 pulses/kwh to 20,000 pulses/kwh. ? example: to set 1,500 pulses/kwh, the new e-pulse con- stant will be 1,500 inaccuracy of the e-pulse higher e-pulse constant is always desirable as it reduces the testing time. however, increase in pulses/kwh may increases the error at higher power. the error can be calculated by the given formula. general note about calibration ? it should be noted that adsst-em-3035 does not have any permanent memory and hence all the calibration data are to be stored by the microcontroller and provided to the dsp at the time of power up. ? before starting the calibration the meter should be supplied with the default calibration constants as specified in the table iii.
rev. 0 adsst-em-3035 e19e table xii. maximum error (power and energies) current voltage pf min typ max unit 0.01 in < i < 0.05 in v n 1.0 ? ? = = = =
rev. 0 ?0 c02740??1/02(0) printed in u.s.a. adsst-em-3035 table xvi. harmonic distortion error current current min typ max unit 10% of third 0. 05 in < i < i max 0.05 0.1 % harmonic table xvii. reverse phase sequence error current voltage min typ max unit 0.1 in v n 0.05 % table xviii. voltage unbalance error current voltage min typ max unit in v n 15 0.1 0.2 % table xix. starting current voltage min typ max unit v n 0.0007 0.001 in electrical characteristics of adsst-em-3035 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v to 7 v input voltage . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature . . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c recommended operating conditions a grade b grade parameters min max min max unit v dd 707v temperature 0 +70 ?0 +85 c ordering codes a grade: adsst-em-3035-bst b grade: adsst-em-3035-kst outline dimensions ordering guide temperature model range model included package option adsst-em-3035k 0 to +70? adsst-2185kst-133 su-100 adsst-73360ar rw-28 100-lead thin plastic quad flat package [tqfp] (su-100) dimensions shown in millimeters 0.27 0.22 0.17 top view (pins down) 1 25 26 49 76 100 75 50 14.00 sq 16.00 sq 0.50 bsc 7 0 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max compliant to jedec standards ms-026aed-hd center figures are typical unless otherwise noted 28-lead standard small outline package [soic] wide body (rw-28) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10

▲Up To Search▲

Price & Availability of SST-SALEM-3T

	To Download SST-SALEM-3T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .